1. Field
This disclosure relates generally to logic state retention, and more specifically, to a circuit having logic state retention during a power-down mode and method therefor.
2. Related Art
Lower power consumption has been gaining importance in integrated circuit data processing systems due to, for example, wide spread use of portable and handheld applications. Most circuits in handheld devices are typically off (e.g., in an idle or deep sleep mode) for a significant portion of time, consuming only leakage power. As transistor leakage currents increase with finer geometry manufacturing processes, it becomes more difficult to meet chip leakage targets using traditional power reduction techniques. Therefore, reducing leakage current is becoming an increasingly important factor in extending battery life.
One method that has been used to reduce leakage current of integrated circuits is to increase the threshold voltage of the transistors in the device. However, simply increasing the threshold voltage of the transistors may result in unwanted consequences such as slowing the operating speed of the device and limiting circuit performance.
Another method that has been used to reduce leakage current is to “power gate”, or cut off power to certain blocks of the integrated circuit that are not needed when the integrated circuit is in a low power mode. However, in doing so, the state of the circuit block is lost. In many circuit blocks state retention is needed in order to prevent loss of important information and allow for proper circuit operation and performance when recovering from a low power mode. Many state retention flip-flop circuits incorporate an additional storage mechanism to retain a logic state during power gating. However, the additional devices that are required to implement the state retention storage mechanism can significantly increase the amount of surface area on an integrated circuit.
Another way to provide state retention during a power gate mode without using an additional storage mechanism is to provide a reduced power supply voltage to the flip-flops while removing the power supply voltage from the rest of the circuit. The reduced power supply voltage further reduces a leakage current, thus lowering power consumption even more. However, this method for power gating requires the routing of two or more power supplies, and at least two relatively large header and/or footer devices for each routing that take up a significant amount of surface area on integrated circuit.
Therefore, what is needed is a circuit and method that solves the above problems.